The Limits of Panel Packaging

The semiconductor industry is debating whether panel-based packaging will replace wafer-level technologies to meet the demands of massive AI processors. According to Kevin Zhang, TSMC’s senior vice president of business development and global sales and deputy co-COO, wafer-level technology remains superior in interconnection density for the most complex architectures.

The industry often assumes that panel-based processes will replace CoWoS because they promise larger package sizes—moving from 120mm x 150mm to 310mm x 310mm—at lower costs. This assumption ignores the fundamental gap in technological capability. Zhang notes that the geometric complexity handled by panel-based processes is nowhere near the capability of wafer-level technology.

This distinction matters because the roadmap for AI compute relies on density, not just surface area. While CoPoS offers a way to use panel-based processes to drive interposer scaling, it cannot match the advanced lithography, etching, and deposition tools used in wafer-level packaging. These wafer-level tools are the same ones used to manufacture logic chips themselves.

TSMC is not abandoning future options, but they are doubling down on the scalability of existing methods. The company's CoWoS roadmap retains significant runway through wafer-level integration. This approach allows for scaling CoWoS to 14X and provides the ability to integrate 58 large reticle-sized dies into a single unit.

The takeaway is clear: size is not the only metric of progress in advanced packaging. While panel-level integration offers larger footprints, the industry's most critical work continues at the wafer level, where precision and density remain the primary drivers of AI performance.

Watch the development of interposer scaling to see if panel-based processes can ever bridge the complexity gap.