The End of Data Shuttling

The energy cost of AI is largely a logistics problem. Current hardware architecture forces data to travel between separate sensing, memory, and processing components, a constant shuttling of information that drains power and limits efficiency.

Researchers at Oregon State University have developed a light-sensitive digital memory device that integrates these functions into a single phototransistor to reduce the energy cost of future AI hardware. By combining sensing, memory, and signal processing inside one unit, the device performs work right where light hits the sensor.

This architecture mimics a fundamental biological process: the brain's ability to selectively forget. The device is designed to strengthen important memories while allowing less useful information to fade over time.

The hardware utilizes a phototransistor composed of two materials. An oxide semiconductor forms the transistor channel, while a photosensitive organic layer sits on top to absorb light and generate electrical charges. When light hits the device, some charges become trapped in the organic layer. These trapped charges continue to influence the current in the semiconductor channel even after the light source is gone, allowing the device to retain a memory of the optical signal.

The significance lies in the control of this memory. By applying a small electrical gate voltage, researchers can move these trapped charges closer to or farther from the transistor channel. Moving them closer strengthens the memory and extends its duration; moving them farther away weakens the effect.

This development shifts the paradigm of machine perception from centralized processing to edge-level intelligence. If processing happens at the sensor level, the need to move massive datasets across hardware blocks diminishes. For the industry, this suggests a future where AI sensors are not just passive observers, but active, energy-efficient processors capable of filtering information before it ever reaches a central unit.

The question for hardware architects is no longer just how much compute we can pack into a chip, but how much movement we can eliminate from the architecture entirely.