Intel Foundry's Roadmap Expansion

Intel Foundry is moving beyond simple node scaling to a strategy of differentiated process technologies. At the VLSI 2026 Symposium, Intel provided an update on its technology roadmap, introducing the 18A-P derivative alongside the continued maturation of Intel 18A.

The company is currently ramping its 18A process in two U.S. fabrication facilities. This node integrates RibbonFET gate-all-around transistors and PowerVia backside power delivery, technologies essential for advanced logic scaling. While 18A is already powering multiple client products, data center applications are expected to follow. Intel reported that defect density is declining ahead of internal projections.

The introduction of 18A-P represents a shift toward performance-enhanced derivatives rather than simple process shrinks. This new derivative maintains backward compatibility with existing 18A designs but introduces improved power delivery structures and enhanced thermal characteristics. The measurable improvements in power, performance, and area (PPA) include:

• Up to 18% lower power consumption at iso-performance.
• Approximately 9% higher performance at iso-power based on a fully routed Arm core test vehicle.
• 20-40% improvements in thermal resistance.
• 10-30% lower via resistance.

This approach mirrors the execution model used by TSMC, where success relies on communicating a clear roadmap and executing against it to build ecosystem trust. Intel is attempting to use these technical differentiators to strengthen its position in the foundry market. The ability to deliver measurable PPA gains through specialized derivatives like 18A-P suggests that the future of foundry competition will be won on architectural refinement, not just node shrinks.

The industry should watch whether Intel can maintain this execution discipline as it scales 18A across its manufacturing footprint.